FPGA——Electronic Engineering
Date:2016-09-05 Views:3702Secondary
"Gowin claims that one innovation in the GW1N family is this random-access on-chip user flash memory that can be accessed 'just as normal NOR flash memory.' (Lattice provides up to 256Kb of user-flash, but not random access, and Altera provides 12K-736K, also not random access.) For many applications, this on-chip, random access NVM could be a game-changer." —— Electronic Engineering Journal's reader
Let me guess, you've never heard of Gowin Semiconductor? You have a lot of company. Gowin, based in Guangdong, China, has been operating quietly for only the past 20 months. Now, they are announcing their - wait, what? SECOND FPGA family? Wow, that's fast. Most FPGA startups take years to announce their first attempts.
Maybe we should step back for a second and survey the scene here.
Gowin, backed by Chinese private investors, has R&D in 3 Chinese cities: Shanghai, Jinan (Shandong), and Foshan (Guangdong). They have a wholly owned US subsidiary - Melody Semiconductor, LLC, that provides marketing and other consulting services. Their first device family, GW2A, was launched earlier this year. GW2A is a mid-range FPGA family with four devices ranging from 21K to 98K LUTs.
Gowin markets primarily to Chinese companies, so their marketing hasn’t had a lot of need to reach the West. And, they're taking modest, focused steps on their road ｉｎｔｏ the programmable logic world, so they haven't yet ruffled the feathers or invoked the marketing machine wrath of the likes of Xilinx and Altera. They're working quietly and quickly under the radar, developing specific devices for specific markets.
In reality, Gowin is much more likely to competitively bump ｉｎｔｏ the likes of Lattice Semiconductor, Microsemi, or QuickLogic than Altera and Xilinx. Their devices are in the small-to-mid-size range, and their target markets align more with those of the lower-density competitors in the “FPGA” space.
This week, Gowin is announcing their new GW1N family - a two-device lineup, with 1K and 9K LUTs - of non-volatile FPGAs fabricated with TSMC's 55nm embedded flash process. These devices probably line up competitively most closely with Lattice Semiconductor's MachXO3 family (640 to 6.9K LUT non-volatile FPGAs) and with Altera's MAX 10 (2K to 50K LUT non-volatile FPGAs). Gowin claims the new devices are targeting the consumer, industrial, and automotive markets, among others.
Let's take a look at the datasheets and see how GW1N compares with the most likely competition: The LUT counts weigh in at 1,152 and 8,640 LUTs (vs 640-6,900 for Lattice, and 2K-50K for Altera). Block RAM at 72K-198K (vs 64K-240K for Lattice and 108K-1,638K for Altera). User flash non-volatile memory (NVM) at 96K-1,792K. NOTE: Gowin claims that one innovation in the GW1N family is this random-access on-chip user flash memory that can be accessed “just as normal NOR flash memory.” (Lattice provides up to 256Kb of user-flash, but not random access, and Altera provides 12K-736K, also not random access.) For many applications, this on-chip, random access NVM could be a game-changer. GW1N also provides 0-20 18x18 hardware multiplier blocks (vs none for Lattice and 16-144 for Altera). Max user I/O is 120-272 pins (28-335 for Lattice, and 27-500 for Altera).
All these numbers add up to GW1N offering a respectable alternative to Lattice and Altera non-volatile devices with the random-access user flash as a key differentiator. Since Gowin is based in China, they should also have a significant home-field advantage in that market against their US competitors.
But what about tools? Gowin offers a full-dedicated suite of design tools - with the centerpiece being Synopsys SynplifyPro, so you won't be left to struggle with a new-on-the-scene immature software offering - on the synthesis side, at least. Gowin says that their tools already support GW1N, so users can get started designing right away, with the first engineering samples of devices expected in Q4, 2015.
We have written many times about the challenges of starting a new FPGA company. The attempts and failures lists have almost exactly a 1:1 correlation, with Achronix, and now Gowin, being the only current FPGA startups still alive and kicking, and a handful of other startups such as SiliconBlue with technology still in use by those who acquired them. The reasons for failure are almost always the same - immature tool flows, lack of IP, and weak technical marketing support contributing to a lack of customer confidence in designing-in devices.
Gowin has a couple of things going for them, however. First, by being a Chinese company marketing primarily to Chinese customers, they have a distinct advantage in that potentially lucrative market. Second, by partnering with Synopsys for key parts of the tool flow, they avoid one of the major traps that have killed many FPGA startups. Third, by keeping their focus narrow and by building smaller, less elaborate devices, they significantly reduce the challenges and cost of bringing their product to market. Finally, by avoiding the strongholds of the Xilinx/Altera duopoly, they avoid the daunting challenges of head-to-head competition against those two juggernauts. True, they are competing directly with Altera's MAX 10 offering, but MAX 10 is certainly not Altera's bread-and-butter, and, with the impending Intel acquisition, Altera's marketing armies probably have bigger fish to fry.
It is worth noting that small- and mid-size FPGAs never directly compete with their larger, fancier namesakes. The target applications are so different that it is almost inconsequential that the devices share the same names. With that in mind, we are actually seeing a lively resurgence in competition in the lower end, with only minimal participation and interference from the big two programmable logic companies. Now, with Gowin bringing a new challenge from China, it will be interesting to watch how that market evolves.
